Keertana Settaluri, Ameer Haj-Ali, Qijing Huang, Kourosh Hakhamaneshi
Domain specialization under energy constraints in deeply-scaled CMOS has been driving the need for agile development of Systems on a Chip (SoCs). While digital subsystems have design flows that are conducive to rapid iterations from specification to layout, analog and mixed-signal modules face the challenge of a long human-in-the-middle iteration loop that requires expert intuition to verify that post-layout circuit parameters meet the original design specification. Existing automated solutions that optimize circuit parameters for a given target design specification have limitations of being schematic-only, inaccurate, sample-inefficient or not generalizable. This work presents AutoCkt, a machine learning optimization framework trained using deep reinforcement learning that not only finds post-layout circuit parameters for a given target specification, but also gains knowledge about the entire design space through a sparse subsampling technique. Our results show that for multiple circuit topologies, AutoCkt is able to converge and meet all target specifications on at least 96.3% of tested design goals in schematic simulation, on average 40X faster than a traditional genetic algorithm. Using the Berkeley Analog Generator, AutoCkt is able to design 40 LVS passed operational amplifiers in 68 hours, 9.6X faster than the state-of-the-art when considering layout parasitics.
Katerina Papadopoulou
As devices are scaling in the deep-submicron regime variability rises and becomes more complex, making traditional statistical modeling insufficient. Circuit designers need to account for design-specific effects of variability in order to accurately optimize for yield, which normally requires some statistical modeling expertise. This project develops a methodology for simple, fast, design-specific yield optimization that is accessible to the circuit designer. The methodology uses backpropagation of variance and commercial convex programming tools to customize the models to a specific design. In order to validate our centering algorithm for AMS circuits, test structures were designed in 28nm FDSOI technology, including device characterization and comparator characterization structures. The goal is to shorten the design manufacturing proccess by improving the yield prediction of the models at an early design stage.
Amy Whitcombe
Performance variability presents a major challenge to reliably implementing large arrays of mixed-signal circuits in scaled technologies. To determine the feasibility of building readout integrated circuits (ROICs) for imaging detector arrays in 28nm bulk CMOS, we developed a chip to characterize performance variability in areas specifically relevant to image sensors: leakage current and random telegraph signaling (RTS) noise. Sufficiently high leakage current in per-pixel reset switch devices can lead to pixel failure, while RTS noise can introduce perceptible image inaccuracies due to pixel blinking. The test chip is currently being characterized.
Rachel Hochman
The purpose of this research is to build a 20GS/s 7bits ENOB time-interleaved ADC in 28nm FDSOI. In this kind of architecture several converters are interleaved and sample the signal in turns at a lower sampling frequency. In this project the goal is to interleave many SAR ADCs that operate in their maximum efficiency zone. The privileged approach is to design them with a thermal noise limited resolution and to drive them with the input signal without using a front-end track-and-hold.
However this kind of architecture suffers from mismatches between the individual converters that degrade the TIADC SNDR. They can be classified in different categories: offset, gain, skew and bandwidth mismatches. One challenge of this research is to develop mixed signal background calibration schemes to correct the mismatch errors, with a special focus on bandwidth mismatch.