Chip Gallery Variability

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Designers:

Liang-Teck Pang

Tapeout:

ST 90nm, December 2004

Description:

Die photo of the 90nm testchip used to investigate the effects of layout on cmos performance. This chip contains an array of ring oscillators and off-transistors. Measurement of the ring oscillator frequencies and the off-transistor leakage currents are collected and analysed to obtain variation and spatial correlation statistics.

Related publications:

VLSI 2006