Chip Gallery Sigma-Delta

Designers:

Renaldi Winoto

Tapeout:

ST 90nm, July 2008

Description:

This chip implements a highly reconfigurable RF receiver based on a down-converting sigma-delta A/D. An input RF signal is down-coverted to baseband using a passive mixed within a second-order sigma-delta A/D. An SNR of > 59 dB is measured accross a 4-MHz bandwidth at center frequencies ranging from 400MHz to 1.7GHz. An IIP3 of >+19dBm is measured.

Related publications:

VLSI 2009