Chip Gallery SAR ADC

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Designers:

Dusan Stepanovic

Tapeout:

ST 65nm, November 2011

Description:

This chip contains a 2.8GS/s 44.6mW time-interleaved ADC achieving 50.9dB SNDR and 3dB effective resolution bandwidth of 1.5GHz in 65nm CMOS.

Related publications:

VLSI 2012