Chip Gallery Raven 3

Designers:

Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu

Tapeout:

ST 28nm FDSOI, September 2013

Description:

This work demonstrates a RISC-V vector microprocessor implemented in 28nm FDSOI with fully-integrated non-interleaved switched-capacitor DCDC (SC-DCDC) converters and adaptive clocking that generates four on-chip voltages between 0.5V and 1V using only a 1.0V core and 1.8V IO voltage input. The design pushes the capabilities of SC-DCDC conversion by enabling fast transitions (20ns), high conversion efficiency (80-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

Related publications:

VLSI 2015, HotChips 2015