Chip Gallery Pipelined ADC

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Designers:

Yun Chiu

Tapeout:

ST 130nm, January 2003

Description:

A 12MS/s, 14-bit pipeline ADC with 103dB SFDR and 75.5dB of SNDR. It features SHA-less architecture, pseudo-differential nested gain boosting amplifires, passive error averaging and amplier sharing.