Chip Gallery Pipelined ADC

  1. Home
  2. Chip Gallery
  3. Pipelined ADC

Designers:

Bill Tsang

Tapeout:

ST 130nm, July 2007

Description:

This project investigates the possibility of enhancing ADC performance using digital signal-processing techniques. It uses a slow, but accurate, sigma-delta A/D as a reference to correct the errors from a high-speed pipelined A/D. The analog circuits, comprising of a sigma-delta A/D and a pipelined A/D has been implemented in 130nm standard digital CMOS process. The digital signal processor is implemented off-chip using an FPGA.